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Disambiguation of "Chattopadhyay, Santanu"

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Fault Coverage Enhancement via Weighted Random Pattern Generation in BIST Using a DNN-Driven-PSO Approach.

, , , , , and . ICIT, page 228-233. IEEE, (2019)

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Anupam Chattopadhyay

Santanu Sarma

Santanu Mukherjee

Dhrupadi Chattopadhyay

Santanu Pal

 

Other publications of authors with the same name

An ATE assisted DFD technique for volume diagnosis of scan chains., , , and . DAC, page 31:1-31:6. ACM, (2013)A hardware based low temperature solution for VLSI testing using decompressor side masking., , , and . ISCAS, page 637-640. IEEE, (2015)Confidence Based Power Aware Testing., , , and . ISED, page 62-66. IEEE, (2012)Application Mapping Onto Mesh-of-Tree Based Network-on-Chip Using Discrete Particle Swarm Optimization., , and . ISED, page 172-176. IEEE, (2012)An ILP-based floorplan-aware path synthesis technique for Application-Specific NoC design., and . RAIT, page 543-548. IEEE, (2016)Reliability-aware application mapping onto mesh based Network-on-Chip., , and . Integr., (2018)Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution., , and . Integr., (2018)Improving Security of Logic Encryption in Presence of Design-for-Testability Infrastructure., , and . ISCAS, page 1-5. IEEE, (2019)A Deep Neural Network Augmented Approach for Fixed Polarity AND-XOR Network Synthesis., , , , , and . TENCON, page 2189-2193. IEEE, (2019)Fault Coverage Enhancement via Weighted Random Pattern Generation in BIST Using a DNN-Driven-PSO Approach., , , , , and . ICIT, page 228-233. IEEE, (2019)