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3D domain wall memory-cell structure, array architecture and operation algorithm with anti-disturbance.

Y. Fu, K. Yang, B. Chen, and Y. Lin. Microelectron. J., (2017)

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Yinyin Yuan

Lin Lin

Other publications of authors with the same name

A BIST scheme for high-speed Gain Cell eDRAM.B. Yan, Y. Xie, R. Yuan, and Y. Lin. ASICON, page 244-247. IEEE, (2011)3D domain wall memory-cell structure, array architecture and operation algorithm with anti-disturbance.Y. Fu, K. Yang, B. Chen, and Y. Lin. Microelectron. J., (2017)A 2Mb ReRAM with two bits error correction codes circuit for high reliability application.J. Yang, Y. Meng, X. Xue, R. Huang, Q. Zhou, J. Wu, and Y. Lin. ASICON, page 1-4. IEEE, (2013)3D vertical RRAM architecture and operation algorithms with effective IR-drop suppressing and anti-disturbance.Y. Lin, R. Yuan, X. Xue, and B. Chen. ISCAS, page 377-380. IEEE, (2015)A small area and low power true random number generator using write speed variation of oxidebased RRAM for IoT security application.J. Yang, Y. Lin, Y. Fu, X. Xue, and B. Chen. ISCAS, page 1-4. IEEE, (2017)A low cost and high reliability true random number generator based on resistive random access memory.J. Yang, J. Xu, B. Wang, X. Xue, R. Huang, Q. Zou, J. Wu, and Y. Lin. ASICON, page 1-4. IEEE, (2015)Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform.K. Yang, Y. Zhao, J. Yang, X. Xue, Y. Lin, and J. Bae. ASICON, page 1-4. IEEE, (2015)ANS: Assimilating Near Similarity at High Accuracy for Significant Deduction of CNN Storage and Computation.W. Wang, X. Zhong, M. Li, Z. Li, and Y. Lin. IEEE Access, (2023)Low-Power Variation-Tolerant Nonvolatile Lookup Table Design.X. Xue, J. Yang, Y. Lin, R. Huang, Q. Zou, and J. Wu. IEEE Trans. Very Large Scale Integr. Syst., 24 (3): 1174-1178 (2016)A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction.X. Xue, W. Jian, J. Yang, F. Xiao, G. Chen, X. Xu, Y. Xie, Y. Lin, R. Huang, Q. Zhou and 1 other author(s). VLSIC, page 42-43. IEEE, (2012)

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Disambiguation of "Lin, Yinyin"

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3D domain wall memory-cell structure, array architecture and operation algorithm with anti-disturbance.

Please choose a person to relate this publication to

Yinyin Yuan

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lin, Yinyin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 3D domain wall memory-cell structure, array architecture and operation algorithm with anti-disturbance.

Please choose a person to relate this publication to

Yinyin Yuan

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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3D domain wall memory-cell structure, array architecture and operation algorithm with anti-disturbance.