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Disambiguation of "Tao, Yaoyu"

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An Automated FPGA-Based Framework for Rapid Prototyping of Nonbinary LDPC Codes.

, and . ISCAS, page 1-5. IEEE, (2019)

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Tao Tao

Christina Taouss

Tao Huu Phung

Madelaine Taoubi

Xue Tao

 

Other publications of authors with the same name

A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating., , and . IEEE J. Solid State Circuits, 50 (2): 464-475 (2015)A 4.68Gb/s belief propagation polar decoder with bit-splitting register file., , , and . VLSIC, page 1-2. IEEE, (2014)Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes., , and . CoRR, (2022)HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer., and . MICRO, page 845-856. ACM, (2021)High-Throughput Split-Tree Architecture for Nonbinary SCL Polar Decoder., and . ISCAS, page 2057-2061. IEEE, (2022)Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize Search., , , , , and . FPGA, page 177-183. ACM, (2023)eNODE: Energy-Efficient and Low-Latency Edge Inference and Training of Neural ODEs., , and . HPCA, page 802-813. IEEE, (2023)Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 59 (4): 1235-1245 (April 2024)An Automated FPGA-Based Framework for Rapid Prototyping of Nonbinary LDPC Codes., and . ISCAS, page 1-5. IEEE, (2019)A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture., , and . IEEE J. Solid State Circuits, 56 (2): 612-623 (2021)