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Disambiguation of "Yamamoto, Takaya"

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A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver.

, , , , , , , and . IEEE J. Solid State Circuits, 49 (11): 2503-2514 (2014)

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Masaaki Yamamoto

Shelby Yamamoto

Kenji Yamamoto

Jun Yamamoto

Gaku Yamamoto

 

Other publications of authors with the same name

A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver., , , , , , , and . IEEE J. Solid State Circuits, 49 (11): 2503-2514 (2014)A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range., , , , and . IEEE J. Solid State Circuits, 49 (5): 1173-1183 (2014)Correction to Ä 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range"., , , , and . IEEE J. Solid State Circuits, 50 (2): 619 (2015)A 63-mA 112/94-dB DR IF bandpass ΔΣ modulator with direct feed-forward and double sampling., , and . CICC, page 61-64. IEEE, (2007)Computational evaluation of a market-oriented programming method for distributed energy management systems., , , , , and . SMC, page 650-655. IEEE, (2007)Black Hole Attack Prevention Method Using Dynamic Threshold in Mobile Ad Hoc Networks., and . FedCSIS, volume 11 of Annals of Computer Science and Information Systems, page 797-802. (2017)Quality estimation for Japanese Haiku poems using Neural Network., , , , , , and . SSCI, page 1-8. IEEE, (2016)A 63 mA 112/94 dB DR IF Bandpass ΔΣ Modulator With Direct Feed-Forward Compensation and Double Sampling., , and . IEEE J. Solid State Circuits, 43 (8): 1783-1794 (2008)A 5 mm2 40 nm LP CMOS Transceiver for a Software-Defined Radio Platform., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 45 (12): 2794-2806 (2010)A 5mm2 40nm LP CMOS 0.1-to-3GHz multistandard transceiver., , , , , , , , , and 1 other author(s). ISSCC, page 458-459. IEEE, (2010)