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Disambiguation of "Matsuura, Tatsuji"

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A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver.

, , , , , , , and . IEEE J. Solid State Circuits, 49 (11): 2503-2514 (2014)

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Takeshi Matsuura

 

Other publications of authors with the same name

A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm., , , , , , , , , and 4 other author(s). IEICE Trans. Electron., 90-C (6): 1181-1188 (2007)A 63 mA 112/94 dB DR IF Bandpass ΔΣ Modulator With Direct Feed-Forward Compensation and Double Sampling., , and . IEEE J. Solid State Circuits, 43 (8): 1783-1794 (2008)Digital Calibration Algorithm of Conversion Error Influenced by Parasitic Capacitance in C-C SAR-ADC Based on γ-Estimation., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 104-A (2): 516-524 (2021)ΔΣ ADCs and Converter Techniques., and . ISSCC, page 236-237. IEEE, (2007)A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components., , , , , and . ASP-DAC, page 15-16. IEEE, (2017)A 12-Bit 3.3MS/S pipeline cyclic ADC with correlated level shifting technique., , , , , , and . ISPACS, page 602-605. IEEE, (2017)Non-binary cyclic and binary SAR hybrid ADC., , , and . MIXDES, page 105-109. IEEE, (2017)A 63-mA 112/94-dB DR IF bandpass ΔΣ modulator with direct feed-forward and double sampling., , and . CICC, page 61-64. IEEE, (2007)1-GHz Input bandwidth 6-bit under-sampling A/D converter for UWB-IR receiver., , , , , , , , , and 1 other author(s). ESSCIRC, page 163-166. IEEE, (2007)A 0.8V 14bit 294kSPS non-binary cyclic ADC in 65nm SOTB CMOS technology., , , , , , and . ISPACS, page 1-2. IEEE, (2021)