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Virtual Prototype based Analysis of Neural Network Cache Behavior for Tiny Edge Device.

, , , and . FDL, page 1-6. IEEE, (2022)

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Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing., , and . IEEE Embed. Syst. Lett., 14 (4): 195-198 (2022)Specification-Based Symbolic Execution for Stateful Network Protocol Implementations in IoT., , and . IEEE Internet Things J., 10 (11): 9544-9555 (June 2023)An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes., , and . DATE, page 218-221. IEEE, (2021)Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study., , , , and . DSD, page 134-141. IEEE, (2022)Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction., , , and . Int. J. Softw. Tools Technol. Transf., 21 (5): 545-565 (2019)RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms., , and . ATVA, volume 12302 of Lecture Notes in Computer Science, page 543-549. Springer, (2020)Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents., , , , and . DSD, page 129-136. IEEE, (2019)Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime., , , and . ICCD, page 312-315. IEEE, (2020)Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype., , and . ACM Great Lakes Symposium on VLSI, page 193-197. ACM, (2022)Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing., , and . DAC, page 667-672. IEEE, (2021)