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Disambiguation of "Tenace, Valerio"

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Row-based body-bias assignment for dynamic thermal clock-skew compensation.

, , , , , and . Microelectron. J., 45 (5): 530-538 (2014)

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Valerio Ketmaier

Valerio Cosentino

Valerio Maggio

Valerio Lucarini

Valerio Avitabile

 

Other publications of authors with the same name

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization., , , , , , , , , and 31 other author(s). CoRR, (2020)Quasi-exact logic functions through classification trees., and . Integr., (2018)Ultra-low power circuits using graphene p-n junctions and adiabatic computing., , , , and . Microprocess. Microsystems, 39 (8): 962-972 (2015)Activation-Kernel Extraction through Machine Learning., and . NGCAS, page 5-8. IEEE, (2017)Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits., , , and . VLSI-SoC, page 1-6. IEEE, (2016)Multiplication by Inference using Classification Trees: A Case-Study Analysis., , and . ISCAS, page 1-5. IEEE, (2018)Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization., , , , , , , , , and 31 other author(s). DATE, page 1026-1031. IEEE, (2021)Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (12): 1111-1115 (2016)Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits., and . VLSI-SoC, page 149-154. IEEE, (2018)Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits., , , and . VLSI-SoC (Selected Papers), volume 508 of IFIP Advances in Information and Communication Technology, page 60-82. Springer, (2016)