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The Cost of Flexibility: Embedded versus Discrete Routers in CGRAs for HPC.

, , , , , and . CLUSTER, page 347-356. IEEE, (2022)

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Exploration of Compute vs. Interconnect Tradeoffs in CGRAs for HPC., , , , , and . HEART, page 59-68. ACM, (2023)Exploring Inter-tile Connectivity for HPC-oriented CGRA with Lower Resource Usage., , , , , , and . FPT, page 1-4. IEEE, (2022)Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC., , , , , , , and . IPDPS Workshops, page 452-459. IEEE, (2023)Compiler Software Coherent Control for Embedded High Performance Multicore., , , , and . IEICE Trans. Electron., 103-C (3): 85-97 (2020)Efficient Queue-Balancing Switch for FPGAs., , , and . FPT, page 1-5. IEEE, (2021)An Architecture- Independent CGRA Compiler enabling OpenMP Applications., , , , and . IPDPS Workshops, page 631-638. IEEE, (2022)The Cost of Flexibility: Embedded versus Discrete Routers in CGRAs for HPC., , , , , and . CLUSTER, page 347-356. IEEE, (2022)Exploration Framework for Synthesizable CGRAs Targeting HPC: Initial Design and Evaluation., , , , , and . IPDPS Workshops, page 639-646. IEEE, (2022)Multicore Cache Coherence Control by a Parallelizing Compiler., , , , , and . COMPSAC (1), page 492-497. IEEE Computer Society, (2017)Software Cache Coherent Control by Parallelizing Compiler., , , , , , , and . LCPC, volume 11403 of Lecture Notes in Computer Science, page 17-25. Springer, (2017)