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Memory reliability improvements based on maximized error-correcting codes.

, , and . European Test Symposium, page 1-6. IEEE Computer Society, (2012)

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Deterministic logic BIST for transition fault testing., , , and . IET Comput. Digit. Tech., 1 (3): 180-186 (2007)Efficient Pattern Mapping for Deterministic Logic BIST., , , , , and . ITC, page 48-56. IEEE Computer Society, (2004)Error-correction schemes with erasure information for fast memories., and . ETS, page 1-6. IEEE Computer Society, (2013)System-level hardware-based protection of memories against soft-errors., , , , and . DATE, page 1222-1225. IEEE, (2009)Error Correction Schemes with Erasure Information for Fast Memories., , and . J. Electron. Test., 30 (2): 183-192 (2014)Error prediction based on concurrent self-test and reduced slack time., , , , and . DATE, page 1626-1631. IEEE, (2011)Shadow-scan design with low latency overhead and in-situ slack-time monitoring., , , , , , and . ETS, page 1-6. IEEE, (2014)Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics., , , , and . ITC, page 1-9. IEEE, (2017)Programmable extended SEC-DED codes for memory errors., , , and . VTS, page 140-145. IEEE Computer Society, (2011)Deterministic Logic BIST for Transition Fault Testing., , , and . ETS, page 123-130. IEEE Computer Society, (2006)