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Disambiguation of "Hong, Hao-Chiao"

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8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips.

, , , , , , , , , , , , , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 71 (4): 2304-2308 (April 2024)

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Chiao Yeh

Kwan-Hua Chiao

Hui-Fang Chiao

Shih-Yang Chiao

Yun-Chuang Chiao

 

Other publications of authors with the same name

A Digital Background Calibration Scheme for Pipelined ADCs Using Multiple-Correlation Estimation., and . ISCAS, page 1-5. IEEE, (2018)Gm-C filter with automatic calibration scheme., , , , , and . DDECS, page 206-209. IEEE, (2016)Accurate and Fast On-Wafer Test Circuitry for Device Array Characterization in Wafer Acceptance Test., and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (9): 3467-3479 (2019)A fast-locking all-digital phase locked loop in 90nm CMOS for Gigascale systems., and . ISCAS, page 1134-1137. IEEE, (2014)Testing the Fleischer-Laker switched-capacitor biquad using the diagnosis-after-test procedure., , and . ISOCC, page 179-184. IEEE, (2012)A Fully Integrated BIST \(\Delta \Sigma \) ADC Using the In-Phase and Quadrature Waves Fitting Procedure., and . IEEE Trans. Instrumentation and Measurement, 63 (12): 2750-2760 (2014)Design of a Fault-Injectable Fleischer-Laker Switched-Capacitor Biquad for Verifying the Static Linear Behavior Fault Model., and . Asian Test Symposium, page 62-66. IEEE Computer Society, (2013)An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages., , , and . ATS, page 5-10. IEEE Computer Society, (2017)Design of a 0.20-0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (5): 1840-1852 (2019)A Fully-Settled Linear Behavior Plus Noise Model for Evaluating the Digital Stimuli of the Design-for-Digital-Testability Sigma-Delta Modulators.. J. Electron. Test., 23 (6): 527-538 (2007)