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Automatic generation of loop scheduling for VLIW., , , and . PACT, page 306-309. IFIP Working Group on Algol / ACM, (1995)Dynamic Tolerance Region Computing for Multimedia., , and . IEEE Trans. Computers, 61 (5): 650-665 (2012)A performance evaluation of the multiple bus network for multiprocessor systems., , , , and . SIGMETRICS, page 200-206. ACM, (1983)Novel SRAM bias control circuits for a low power L1 data cache., , , , and . NORCHIP, page 1-6. IEEE, (2012)Picos: A hardware runtime architecture support for OmpSs., , , , and . Future Gener. Comput. Syst., (2015)Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications., , , , , , , , , and 14 other author(s). ACM Trans. Archit. Code Optim., 20 (2): 28:1-28:25 (June 2023)Profile-guided transaction coalescing - lowering transactional overheads by merging transactions., , , , and . ACM Trans. Archit. Code Optim., 10 (4): 50:1-50:18 (2013)Hardware transactional memory with software-defined conflicts., , , , , , , and . ACM Trans. Archit. Code Optim., 8 (4): 31:1-31:20 (2012)RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only)., , , , , and . SIGMETRICS Perform. Evaluation Rev., 39 (3): 19 (2011)Dynamic Cache Partitioning Based on the MLP of Cache Misses., , , and . Trans. High Perform. Embed. Archit. Compil., (2011)