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Hardware transactional memory with software-defined conflicts.

, , , , , , , and . ACM Trans. Archit. Code Optim., 8 (4): 31:1-31:20 (2012)

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Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems., , , and . J. Supercomput., 68 (2): 914-934 (2014)The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors., , , and . IEEE PACT, page 155-164. IEEE Computer Society, (2002)Hardware transactional memory with software-defined conflicts., , , , , , , and . ACM Trans. Archit. Code Optim., 8 (4): 31:1-31:20 (2012)Design of an efficient communication infrastructure for highly contended locks in many-core CMPs., , and . J. Parallel Distributed Comput., 73 (7): 972-985 (2013)A Direct Coherence Protocol for Many-Core Chip Multiprocessors., , and . IEEE Trans. Parallel Distributed Syst., 21 (12): 1779-1792 (2010)Evaluating IA-32 web servers through simics: a practical experience., , and . J. Syst. Archit., 51 (4): 251-264 (2005)Efficient Dir0B Cache Coherency for Many-Core CMPs., , , and . ICCS, volume 18 of Procedia Computer Science, page 2545-2548. Elsevier, (2013)Characterizing Energy Consumption in Hardware Transactional Memory Systems., , , and . SBAC-PAD, page 9-16. IEEE Computer Society, (2010)GLocks: Efficient Support for Highly-Contended Locks in Many-Core CMPs., , and . IPDPS, page 893-905. IEEE, (2011)Fast and Efficient Synchronization and Communication Collective Primitives for Dual Cell-Based Blades., , and . Euro-Par, volume 5704 of Lecture Notes in Computer Science, page 900-911. Springer, (2009)