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HDLs evolve as they affect design methodology for a higher abstraction and a better integration.

. DTIS, стр. 1. IEEE, (2015)

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Kambiz Navabi

Foroogh Navabi-Kermani

 

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A Low Power BIST Architecture for FPGA Look-Up Table Testing., и . VLSI-SOC, стр. 394-397. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models., , , и . CHDL, том A-32 из IFIP Transactions, стр. 569-586. North-Holland, (1993)Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment., , и . Embedded Systems and Applications, стр. 139-143. CSREA Press, (2003)An efficient BIST method for testing of embedded SRAMs., , и . ISCAS (5), стр. 73-76. IEEE, (2001)Programmable Routing Tables for Degradable Torus-Based Networks on Chips., , и . ISCAS, стр. 1065-1068. IEEE, (2007)Back-annotation of gate-level power properties into system level descriptions., и . NEWCAS, стр. 237-240. IEEE, (2014)SCOAP-based Directed Random Test Generation for Combinational Circuits., , , и . EWDTS, стр. 1-5. IEEE, (2019)An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements., , , , , , и . EWDTS, стр. 1-6. IEEE, (2019)Self-Healing Many-Core Architecture: Analysis and Evaluation., и . VLSI Design, (2016)On-Chip Verification of NoCs Using Assertion Processors., , , , и . DSD, стр. 535-538. IEEE Computer Society, (2007)