( en | de | ru )

 

Disambiguation of "Fujita, Masahiro"

Author of the publication

copydeleteadd this publication to your clipboard
Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques.

, and . ISQED, page 297-302. IEEE, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Toko Fujita

Masahiro Noguchi

Buntaro Fujita

Masahiro Ogawa

Masayuki Fujita

 

Other publications of authors with the same name

Tokio: Logic Programming Language Based on Temporal Logic and its Compilation to Prolog., , , and . ICLP, volume 225 of Lecture Notes in Computer Science, page 695-709. Springer, (1986)Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures., , , and . IESS, volume 231 of IFIP Advances in Information and Communication Technology, page 121-134. Springer, (2007)A 48 MHz 880-nW Standby Power Normally-Off MCU with 1 Clock Full Backup and 4.69-μs Wakeup Featuring 60-nm Crystalline In-Ga-Zn Oxide BEOL-FETs., , , , , , , , , and 1 other author(s). VLSI Circuits, page 48-. IEEE, (2019)SDR-4X II: A Small Humanoid as an Entertainer in Home Environment., , , , and . ISRR, volume 15 of Springer Tracts in Advanced Robotics, page 355-364. Springer, (2003)An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults., , and . VTS, page 1-6. IEEE, (2019)Automated data analysis techniques for a modern silicon debug environment., , , and . ASP-DAC, page 298-303. IEEE, (2012)Post-silicon patching for verification/debugging with high-level models and programmable logic., and . ASP-DAC, page 232-237. IEEE, (2012)Formally analyzing fault tolerance in datapath designs using equivalence checking., , , and . ASP-DAC, page 133-138. IEEE, (2016)Improving polynomial datapath debugging with HEDs., , , , and . ETS, page 1-6. IEEE, (2014)Analysis and testing on delays with two time frames.. VLSI-SoC, page 13-18. IEEE, (2015)