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Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks.

H. Homayoun, S. Golshan, E. Bozorgzadeh, A. Veidenbaum, and F. Kurdahi. ISQED, page 499-507. IEEE, (2010)

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V Saile

V Geoffroy

V Wittwer

V Ustinov

V Fendrich

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Preliminary Performance Analysis of the Cedar Multiprocessor Memory System.K. Gallivan, W. Jalby, S. Turner, A. Veidenbaum, and H. Wijshoff. ICPP (1), page 71-75. CRC Press, (1991)Synchronization optimizations for efficient execution on multi-cores.A. Nicolau, G. Li, A. Veidenbaum, and A. Kejariwal. ICS, page 169-180. ACM, (2009)On the performance potential of different types of speculative thread-level parallelism: The DL version of this paper includes corrections that were not made available in the printed proceedings.A. Kejariwal, X. Tian, W. Li, M. Girkar, S. Kozhukhov, H. Saito, U. Banerjee, A. Nicolau, A. Veidenbaum, and C. Polychronopoulos. ICS, page 24. ACM, (2006)Pruning hardware evaluation space via correlation-driven application similarity analysis.R. Cammarota, A. Kejariwal, P. D'Alberto, S. Panigrahi, A. Veidenbaum, and A. Nicolau. Conf. Computing Frontiers, page 4. ACM, (2011)Exploitation of nested thread-level speculative parallelism on multi-core systems.A. Kejariwal, M. Girkar, X. Tian, H. Saito, A. Nicolau, A. Veidenbaum, U. Banerjee, and C. Polychronopoulos. Conf. Computing Frontiers, page 99-100. ACM, (2010)Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency.H. Homayoun, S. Pasricha, M. Makhzan, and A. Veidenbaum. DAC, page 68-71. ACM, (2008)Reducing data cache energy consumption via cached load/store queue.D. Nicolaescu, A. Veidenbaum, and A. Nicolau. ISLPED, page 252-257. ACM, (2003)Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management.H. Homayoun, A. Sasan, J. Gaudiot, and A. Veidenbaum. IEEE Trans. Very Large Scale Integr. Syst., 19 (11): 2081-2094 (2011)Combining Prefetch Control and Cache Partitioning to Improve Multicore Performance.G. Sun, J. Shen, and A. Veidenbaum. IPDPS, page 953-962. IEEE, (2019)AFFIX: Automatic Acceleration Framework for FPGA Implementation of OpenVX Vision Algorithms.S. Taheri, P. Behnam, E. Bozorgzadeh, A. Veidenbaum, and A. Nicolau. FPGA, page 252-261. ACM, (2019)

BibSonomy

Disambiguation of "Veidenbaum, Alexander V."

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Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks.

Please choose a person to relate this publication to

V Saile

V Geoffroy

V Wittwer

V Ustinov

V Fendrich

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Veidenbaum, Alexander V."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks.

Please choose a person to relate this publication to

V Saile

V Geoffroy

V Wittwer

V Ustinov

V Fendrich

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks.