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Checking signal transition graph implementability by symbolic BDD traversal.

, , , , , and . ED&TC, page 325-332. IEEE Computer Society, (1995)

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Formal method for self-timed design., , and . EURO-DAC, page 197-201. EEE Computer Society, (1991)Synthesis of synchronous elastic architectures., , and . DAC, page 657-662. ACM, (2006)Timing-driven N-way decomposition., , and . ACM Great Lakes Symposium on VLSI, page 363-368. ACM, (2009)The Use of Petri Nets for the Design and Verification of Asynchronous Circuits and Systems., , , , and . Journal of Circuits, Systems, and Computers, 8 (1): 67-118 (1998)Compositional performance verification of NoC designs., , , and . MEMOCODE, page 1-10. IEEE, (2012)Automatic microarchitectural pipelining., , , and . DATE, page 961-964. IEEE Computer Society, (2010)Characterizing speed-independence of high-level designs., and . ASYNC, page 44-53. IEEE, (1994)Time elastic digital systems and Petri Nets., and . ACSD, page 1-2. IEEE, (2008)On the Models for Asynchronous Circuit Behaviour with OR Causality., , , , and . Formal Methods Syst. Des., 9 (3): 189-233 (1996)A Scheduling Strategy for Synchronous Elastic Designs., , , and . Fundam. Informaticae, 108 (1-2): 1-21 (2011)