Author of the publication

A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency.

, , , and . Asian Test Symposium, page 306-311. IEEE Computer Society, (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

The Complexity of Fault Detection Problems for Combinational Logic Circuits., and . IEEE Trans. Computers, 31 (6): 555-560 (1982)Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation., , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 301-316. Springer, (2006)An approach to test synthesis from higher level., and . Integr., 26 (1-2): 101-116 (1998)System-on-chip test scheduling with reconfigurable core wrappers., and . IEEE Trans. Very Large Scale Integr. Syst., 14 (3): 305-309 (2006)Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester., , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (7): 790-800 (2007)Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths., , , , and . IEICE Trans. Inf. Syst., 88-D (8): 1940-1947 (2005)Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers., and . IEICE Trans. Inf. Syst., 98-D (10): 1852-1855 (2015)Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability., , , and . IEICE Trans. Inf. Syst., 90-D (1): 296-305 (2007)A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips., , and . IEICE Trans. Inf. Syst., 89-D (4): 1490-1497 (2006)Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents., and . IEICE Trans. Inf. Syst., 100-D (9): 2232-2236 (2017)