( en | de | ru )

 

Disambiguation of "Raghavan, Praveen"

Author of the publication

copydeleteadd this publication to your clipboard
A multi-threaded coarse-grained array processor for wireless baseband.

, , , , , and . SASP, page 102-107. IEEE Computer Society, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Raghavan Vallur

Praveen Konidala

Paurush Praveen

Sarada Raghavan

Raghavan Chinnadurai

 

Other publications of authors with the same name

Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism., , , , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 12-23. Springer, (2006)Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors., , , , and . ACM Trans. Design Autom. Electr. Syst., 12 (4): 41 (2007)Array Interleaving - An Energy-Efficient Data Layout Transformation., , , , and . ACM Trans. Design Autom. Electr. Syst., 20 (3): 44:1-44:26 (2015)Exploiting finite precision information to guide data-flow mapping., , , , and . DAC, page 248-253. ACM, (2010)Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes., , , , , and . DAC, page 51:1-51:6. ACM, (2017)The defect-centric perspective of device and circuit reliability - From individual defects to circuits., , , , , , , , , and 5 other author(s). ESSDERC, page 218-225. IEEE, (2015)CMOS low-power transceivers for 60GHz multi Gbit/s communications., , , , , , , , , and 7 other author(s). CICC, page 1-8. IEEE, (2013)Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures., , , , , , and . Integr., 41 (1): 38-48 (2008)A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (4): 1204-1214 (2017)Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors., , , , , and . J. Signal Process. Syst., 64 (1): 75-92 (2011)