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Disambiguation of "Yang, Rong-Jyi"

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A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit.

, , , , and . IEEE J. Solid State Circuits, 41 (6): 1380-1390 (2006)

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Rong Yang

Chau Rong Yang

Yang Yang

Yang Yang

Yang Yang

 

Other publications of authors with the same name

A 1.25Gbps all-digital clock and data recovery circuit with binary frequency acquisition., and . APCCAS, page 680-683. IEEE, (2008)Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 51-I (12): 2356-2364 (2004)An All-Digital Fast-Locking Programmable DLL-Based Clock Generator., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (1): 361-369 (2008)A wide-range all-digital delay-locked loop using fast-lock variable SAR algorithm., , , and . ISPACS, page 338-342. IEEE, (2012)A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (1): 17-25 (2016)A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet., , and . IEEE J. Solid State Circuits, 39 (8): 1356-1360 (2004)A 200-Mbps∼2-Gbps continuous-rate clock-and-data-recovery circuit., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (4): 842-847 (2006)A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs., and . IEICE Trans. Electron., 88-C (6): 1248-1252 (2005)A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm., and . IEEE J. Solid State Circuits, 42 (2): 361-373 (2007)Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line., , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (3): 567-574 (2015)