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TiN RRAM with Mega-Ω Level LRS for Low Power and Ultrahigh-density Memory.

S. Qin, M. Tung, E. Belliveau, S. Liu, J. Kwon, W. Chen, Z. Jiang, S. Wong, and H. Wong. VLSI Technology and Circuits, page 314-315. IEEE, (2022)

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Simon S Lee

Walter Wong

Limsoon Wong

Wei-chwen Wong

Hoi-Ming Wong

Other publications of authors with the same name

24.2 A 2.5GHz 7.7TOPS/W switched-capacitor matrix multiplier with co-designed local memory in 40nm.E. Lee, and S. Wong. ISSCC, page 418-419. IEEE, (2016)Analysis and Design of a Passive Switched-Capacitor Matrix Multiplier for Approximate Computing.E. Lee, and S. Wong. CoRR, (2016)Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design.B. Kleveland, C. Diaz, D. Vook, L. Madden, T. Lee, and S. Wong. IEEE J. Solid State Circuits, 36 (10): 1480-1488 (2001)Impact of III-V and Ge Devices on Circuit Performance.J. Park, S. Oh, S. Kim, H. Wong, and S. Wong. IEEE Trans. Very Large Scale Integr. Syst., 21 (7): 1189-1200 (2013)Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory.Y. Liauw, Z. Zhang, W. Kim, A. Gamal, and S. Wong. ISSCC, page 406-408. IEEE, (2012)Deep COVID DeteCT: an international experience on COVID-19 lung detection and prognosis using chest CT.E. Lee, J. Zheng, E. Colak, M. Mohammadzadeh, G. Houshmand, N. Bevins, F. Kitamura, E. Altinmakas, E. Reis, J. Kim and 19 other author(s). npj Digit. Medicine, (2021)Factorization for analog-to-digital matrix multiplication.E. Lee, M. Udell, and S. Wong. ICASSP, page 1061-1065. IEEE, (2015)Array Architecture for a Nonvolatile 3-Dimensional Cross-Point Resistance-Change Memory.E. Ou, and S. Wong. IEEE J. Solid State Circuits, 46 (9): 2158-2170 (2011)High-frequency characterization of on-chip digital interconnects.B. Kleveland, X. Qi, L. Madden, T. Furusawa, R. Dutton, M. Horowitz, and S. Wong. IEEE J. Solid State Circuits, 37 (6): 716-725 (2002)A 10-GHz global clock distribution using coupled standing-wave oscillators.F. O'Mahony, C. Yue, M. Horowitz, and S. Wong. IEEE J. Solid State Circuits, 38 (11): 1813-1820 (2003)

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Disambiguation of "Wong, S. Simon"

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8-Layer 3D Vertical Ru/AlOxNy/TiN RRAM with Mega-Ω Level LRS for Low Power and Ultrahigh-density Memory.

Please choose a person to relate this publication to

Simon S Lee

Walter Wong

Limsoon Wong

Wei-chwen Wong

Hoi-Ming Wong

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wong, S. Simon"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 8-Layer 3D Vertical Ru/AlOxNy/TiN RRAM with Mega-Ω Level LRS for Low Power and Ultrahigh-density Memory.

Please choose a person to relate this publication to

Simon S Lee

Walter Wong

Limsoon Wong

Wei-chwen Wong

Hoi-Ming Wong

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

8-Layer 3D Vertical Ru/AlOxNy/TiN RRAM with Mega-Ω Level LRS for Low Power and Ultrahigh-density Memory.