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A simple technique for locating gate-level faults in combinational circuits.

, , и . Asian Test Symposium, стр. 65-70. IEEE Computer Society, (1995)

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Edward J Birkenbeil

Edward J Birkenbeil

Edward J Laarman

Edward Sobel

Edward Fischer

 

Другие публикации лиц с тем же именем

Iterative Combinational Switching Networksߞ General Design Considerations.. IRE Trans. Electron. Comput., 7 (4): 285-291 (1958)Test and Diagnosis Procedure for Digital Networks.. Computer, 4 (1): 17-20 (1971)Open faults in BiCMOS gates., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (5): 567-575 (1995)Pseudorandom Testing., , и . IEEE Trans. Computers, 36 (3): 332-343 (1987)Logic Design of Multivalued I2L Logic Circuits.. IEEE Trans. Computers, 28 (8): 546-559 (1979)Analysis of Logic Circuits with Faults Using Input Signal Probabilities., и . IEEE Trans. Computers, 24 (5): 573-578 (1975)Built-In Verification Test.. ITC, стр. 183-190. IEEE Computer Society, (1982)An Analysis of the Multiple Fault Detection Capabilities of Single Stuck-at Fault Test Sets., и . ITC, стр. 52-58. IEEE Computer Society, (1984)Test Teaching.. ITC, стр. 235. IEEE Computer Society, (1985)An Experimental Study Comparing 74LS181 Test Sets., , и . COMPCON, стр. 384-387. IEEE Computer Society, (1985)