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A simple technique for locating gate-level faults in combinational circuits.

, , and . Asian Test Symposium, page 65-70. IEEE Computer Society, (1995)

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Bounds on Signature Analysis Aliasing for Random Testing., , and . FTCS, page 104-113. IEEE Computer Society, (1991)Pseudorandom Testing., , and . IEEE Trans. Computers, 36 (3): 332-343 (1987)Analysis of Logic Circuits with Faults Using Input Signal Probabilities., and . IEEE Trans. Computers, 24 (5): 573-578 (1975)Logic Design of Multivalued I2L Logic Circuits.. IEEE Trans. Computers, 28 (8): 546-559 (1979)Test and Diagnosis Procedure for Digital Networks.. Computer, 4 (1): 17-20 (1971)Iterative Combinational Switching Networksߞ General Design Considerations.. IRE Trans. Electron. Comput., 7 (4): 285-291 (1958)Open faults in BiCMOS gates., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (5): 567-575 (1995)IC Quality and Test Transparency., and . ITC, page 295-301. IEEE Computer Society, (1988)Refined Bounds on Signature Analysis Aliasing for Random Testing., , and . ITC, page 818-827. IEEE Computer Society, (1991)Verification testing.. DAC, page 495-500. ACM/IEEE, (1982)