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Disambiguation of "Soenen, Eric"

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Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling.

, , , , and . A-SSCC, page 1-3. IEEE, (2021)

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Johan Soenen

Claus Erichsen

Kay Erichsen

Curt Erich

Claus Peter Erichsen

 

Other publications of authors with the same name

A Photovoltaic-Driven and Energy-Autonomous CMOS Implantable Sensor., , , and . IEEE Trans. Biomed. Circuits Syst., 6 (4): 336-343 (2012)Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling., , , , and . A-SSCC, page 1-3. IEEE, (2021)Challenges at 45nm and beyond., , , , and . ICCAD, page 7. IEEE Computer Society, (2008)Physical design methodology for analog circuitsin a system-on-a-chip environment.. ISPD, page 73-74. ACM, (2009)Technology tradeoffs in the design of high performance analog to digital converters.. ICECS, page 7-11. IEEE, (2001)A 65nm, 1.15-0.15V, 99.99% Current-efficient Digital Low Dropout Regulator with Asynchronous Non-linear Control for Droop Mitigation., , , , , , , , , and 3 other author(s). ISCAS, page 1-5. IEEE, (2018)A 2.5 V 10 bit SAR ADC., , , , , and . VLSI Design, page 525-526. IEEE Computer Society, (1997)Practical Considerations for a Digital Inductive-Switching DC/DC Converter With Direct Battery Connect in Deep Sub-Micron CMOS., , , , and . IEEE J. Solid State Circuits, 47 (8): 1946-1959 (2012)A robust digital DC-DC converter with rail-to-rail output range in 40nm CMOS., , , , , and . ISSCC, page 198-199. IEEE, (2010)A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (9): 3373-3383 (2019)