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Multicore-aware parallel temporal blocking of stencil codes for shared and distributed memory.

, , and . IPDPS Workshops, page 1-7. IEEE, (2010)

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Multicore-aware parallel temporal blocking of stencil codes for shared and distributed memory., , and . IPDPS Workshops, page 1-7. IEEE, (2010)Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers., , and . IPDPS, page 1-7. IEEE, (2008)Performance Engineering for a Tall & Skinny Matrix Multiplication Kernels on GPUs., , , and . PPAM (1), volume 12043 of Lecture Notes in Computer Science, page 505-515. Springer, (2019)Physical Oscillator Model for Supercomputing., , and . SC Workshops, page 1229-1235. ACM, (2023)Automatic Throughput and Critical Path Analysis of x86 and ARM Assembly Kernels., , , and . PMBS@SC, page 1-6. IEEE, (2019)Cache Blocking of Distributed-Memory Parallel Matrix Power Kernels., , , , , and . CoRR, (2024)Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers, , and . CoRR, (2007)Hybrid-parallel sparse matrix-vector multiplication with explicit communication overlap on current multicore-based systems, , , and . CoRR, (2011)Performance Engineering for a Tall & Skinny Matrix Multiplication Kernel on GPUs., , , and . CoRR, (2019)Comparison of different propagation steps for lattice Boltzmann methods., , , and . Comput. Math. Appl., 65 (6): 924-935 (2013)