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Disambiguation of "Muramatsu, Atsushi"

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24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits.

, , , , , , , , , , , and . ISQED, page 586-591. IEEE, (2012)

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Atsushi Imai

Atsushi Imai

Alejandro Muramatsu

Yasuyuki Muramatsu

Atsushi Yagi

 

Other publications of authors with the same name

Misleading energy and performance claims in sub/near threshold digital systems., , , , , , , , , and 1 other author(s). ICCAD, page 625-631. IEEE, (2010)12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains., , , , , and . ESSCIRC, page 191-194. IEEE, (2011)Spatial feature detection using a pulse-type hardware neuron model., , and . Syst. Comput. Jpn., 20 (11): 1-10 (1989)24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits., , , , , , , , , and 2 other author(s). ISQED, page 586-591. IEEE, (2012)A Thin, Compact and Maintenance-Free Beacon Transmitter Operating from a 44-lux Photovoltaic Film Harvester., , and . IEICE Trans. Electron., 100-C (6): 584-591 (2017)Effects of on-chip inductance on power distribution grid., , and . ISPD, page 63-69. ACM, (2005)Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (5): 294-298 (2011)