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Event-driven simulation and modeling of an RF oscillator., , and . ISCAS (4), page 641-644. IEEE, (2004)New Concept for Fault Current Limiter With Voltage Restoration Capability., , , , , and . IEEE Trans. Ind. Electron., 67 (12): 10001-10010 (2020)Exploiting temporal idleness to reduce leakage power in programmable architectures., , , and . ASP-DAC, page 651-656. ACM Press, (2005)Estimation of passive mixer output bandwidth using switched-capacitor techniques., , , and . CICC, page 1-4. IEEE, (2013)Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications., , and . CICC, page 861-864. IEEE, (2007)Systolic & semi-systolic digit serial multipliers., and . IEEE Symposium on Computer Arithmetic, page 169-173. IEEE Computer Society, (1987)Hierarchy embedded differential image for progressive transmission using lossless compression., , , and . IEEE Trans. Circuits Syst. Video Techn., 5 (1): 1-13 (1995)Multi-clock domain analysis and modeling of all-digital frequency synthesizers., and . ISCAS, page 153-156. IEEE, (2011)Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 50 (11): 815-828 (2003)All-Digital PLL With Ultra Fast Settling., and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (2): 181-185 (2007)