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ESD protection networks for 3D integrated circuits., , and . 3DIC, page 1-7. IEEE, (2011)Guilty As Charged: Computational Reliability Threats Posed By Electrostatic Discharge-induced Soft Errors., , , , and . DATE, page 156-161. IEEE, (2019)Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects., , , and . DAC, page 752-757. ACM Press, (1996)Interconnect thermal modeling for determining design limits on current density., , , and . ISPD, page 172-178. ACM, (1999)Optimization of SCR for High-Speed Digital and RF Applications in 45-nm SOI CMOS Technology., , , , and . IRPS, page 1-7. IEEE, (2023)iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips., , , , and . DAC, page 548-551. ACM Press, (1996)Noise characterization of static CMOS gates., , , and . DAC, page 888-893. ACM, (2004)Moving signals on and off chip., , , and . CICC, page 585-592. IEEE, (2009)Comprehensive frequency-dependent substrate noise analysis using boundary element methods., , , , , and . ICCAD, page 2-9. ACM / IEEE Computer Society, (2002)Reduced RC Time Constant High Voltage Tolerant Supply Clamp for ESD Protection in 16nm FinFET Technology., , , , and . IRPS, page 1-7. IEEE, (2024)