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i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing.

, , , , , and . IEEE Embed. Syst. Lett., 11 (2): 50-53 (2019)

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i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing., , , , , and . IEEE Embed. Syst. Lett., 11 (2): 50-53 (2019)Live demonstration: ECG sensor interface in a low power SoC for wireless portable ECG monitoring., , , , , , and . BioCAS, page 187. IEEE, (2014)Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures., , , , , and . LASCAS, page 1-4. IEEE, (2022)INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection., , , , , , and . DATE, page 1449-1454. IEEE, (2022)System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms., , , , , , and . ASP-DAC, page 561-566. ACM, (2023)An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 32 (6): 1018-1031 (June 2024)Slack-aware scheduling on Coarse Grained Reconfigurable Arrays., , , and . DATE, page 1513-1516. IEEE, (2011)Lattice-Traversing Design Space Exploration for High Level Synthesis., , and . ICCD, page 210-217. IEEE Computer Society, (2018)MetaWearS: A Shortcut in Wearable Systems Lifecycle with Only a Few Shots., , , , , , , and . CoRR, (2024)Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays., , , , and . ACM Great Lakes Symposium on VLSI, page 223-228. ACM, (2022)