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Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators., , , , and . ISPASS, page 232-234. IEEE, (2021)HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity., , , , , and . MICRO, page 1106-1120. ACM, (2023)Mind the Gap: Attainable Data Movement and Operational Intensity Bounds for Tensor Algorithms., , , and . ISCA, page 150-166. IEEE, (2024)A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy., , and . ISCA, page 376-386. IEEE Computer Society, (2004)Ruby: Improving Hardware Efficiency for Tensor Algebra Accelerators Through Imperfect Factorization., , , , , and . ISPASS, page 254-266. IEEE, (2022)SlicK: slice-based locality exploitation for efficient redundant multithreading., , and . ASPLOS, page 95-105. ACM, (2006)Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach., , , , , and . MICRO, page 754-768. ACM, (2019)SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks., , , , , , , , and . ISCA, page 27-40. ACM, (2017)Demystifying Map Space Exploration for NPUs., , , and . IISWC, page 269-281. IEEE, (2022)Mechanisms for bounding vulnerabilities of processor structures., , and . ISCA, page 506-515. ACM, (2007)