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Disambiguation of "Venkatesan, Rangharajan"

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SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks.

, , , , , , , , and . ISCA, page 27-40. ACM, (2017)

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Venkatesan Guruswami

Chandrasekara Venkatesan

Radhika Venkatesan

Aravind Venkatesan

Venkatesan Guruswami

 

Other publications of authors with the same name

Enabling and Accelerating Dynamic Vision Transformer Inference for Real-Time Applications., , , , and . CoRR, (2022)A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm., , , , , , , and . VLSI Technology and Circuits, page 16-17. IEEE, (2022)VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference., , , , , and . MLSys, mlsys.org, (2021)STAxCache: An approximate, energy efficient STT-MRAM cache., , , , , and . DATE, page 356-361. IEEE, (2017)Reading spin-torque memory with spin-torque sensors., , , , and . NANOARCH, page 40-41. IEEE Computer Society, (2013)A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology., , , , , , , , , and 7 other author(s). Hot Chips Symposium, page 1-24. IEEE, (2019)Cache Design with Domain Wall Memory., , , , , , and . IEEE Trans. Computers, 65 (4): 1010-1024 (2016)Timeloop: A Systematic Approach to DNN Accelerator Evaluation., , , , , , , , , and . ISPASS, page 304-315. IEEE, (2019)Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes., , , and . ACM J. Emerg. Technol. Comput. Syst., 13 (2): 23:1-23:22 (2016)A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm., , , , , , , , and . IEEE J. Solid State Circuits, 58 (4): 1129-1141 (2023)