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Directed Test Generation for Validation of Cache Coherence Protocols.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (1): 163-176 (2019)

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System-on-Chip Security Assertions., and . CoRR, (2020)Automated Test Generation for Activation of Assertions in RTL Models., and . ASP-DAC, page 223-228. IEEE, (2020)Real-time Detection and Localization of DoS Attacks in NoC based SoCs., , and . DATE, page 1160-1165. IEEE, (2019)A Survey of Side-Channel Attacks on Caches and Countermeasures., and . J. Hardw. Syst. Secur., 2 (1): 33-50 (2018)Real-Time Detection and Localization of Distributed DoS Attacks in NoC-Based SoCs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 4510-4523 (2020)Directed Test Generation for Activation of Security Assertions in RTL Models., , and . ACM Trans. Design Autom. Electr. Syst., 26 (4): 26:1-26:28 (2021)Efficient Test Generation for Trojan Detection using Side Channel Analysis., and . DATE, page 408-413. IEEE, (2019)A Survey on Assertion-based Hardware Verification., , , and . ACM Comput. Surv., 54 (11s): 225:1-225:33 (January 2022)Directed Test Generation for Validation of Cache Coherence Protocols., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (1): 163-176 (2019)MaxSense: Side-channel Sensitivity Maximization for Trojan Detection Using Statistical Test Patterns., and . ACM Trans. Design Autom. Electr. Syst., 26 (3): 22:1-22:21 (2021)