Author of the publication

Resilient random modulo cache memories for probabilistically-analyzable real-time systems.

, , , and . IOLTS, page 27-32. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Resilient random modulo cache memories for probabilistically-analyzable real-time systems., , , and . IOLTS, page 27-32. IEEE, (2016)Randomization for Safer, more Reliable and Secure, High-Performance Automotive Processors., , , and . IEEE Des. Test, 36 (6): 39-47 (2019)Modeling the Impact of Process Variations in Worst-Case Energy Consumption Estimation., , , and . DSD, page 601-605. IEEE, (2019)SafeSU: an Extended Statistics Unit for Multicore Timing Interference., , , , , , , and . ETS, page 1-4. IEEE, (2021)Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems., , , , and . RTAS, page 305-316. IEEE Computer Society, (2016)SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping., , , , , , , , and . IOLTS, page 1-7. IEEE, (2021)Non-functional considerations of time-randomized processor architectures.. Polytechnic University of Catalonia, Spain, (2020)Worst-Case Energy Consumption: A New Challenge for Battery-Powered Critical Devices., , , and . IEEE Trans. Sustain. Comput., 6 (3): 522-530 (2021)NOVIA: A Framework for Discovering Non-Conventional Inline Accelerators., , , and . MICRO, page 507-521. ACM, (2021)14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration., , , , , , , , , and 19 other author(s). ISSCC, page 262-264. IEEE, (2024)