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An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits.

, , , , , , , and . DAC, page 1-6. IEEE, (2020)

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A 9T-SRAM in-memory computing macro for Boolean logic and multiply-and-accumulate operations., , , , , , , , and . Microelectron. J., (February 2024)Design of radiation-hardened memory cell by polar design for space applications., , , , , , , , , and 2 other author(s). Microelectron. J., (February 2023)An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset., , , , , , , and . Microelectron. J., (2022)Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 32 (4): 597-608 (April 2024)Offset-Compensation High-Performance Sense Amplifier for Low-Voltage DRAM Based on Current Mirror and Switching Point., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (4): 2011-2015 (2022)In-Memory Multibit Multiplication Based on Bitline Shifting., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (2): 354-358 (2022)Radiation-hardened 14T SRAM cell by polar design for space applications., , , , , , , , , and . IEICE Electron. Express, 20 (13): 20230083 (2023)Architectural Exploration to Address the Reliability Challenges for ReRAM-Based Buffer in SSD., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (1): 226-238 (2019)Read/write margin enhanced 10T SRAM for low voltage application., , , , and . IEICE Electron. Express, 13 (12): 20160382 (2016)Novel radiation-hardened-by-design (RHBD) 14T memory cell for aerospace applications in 65 nm CMOS technology., , , , , , , , , and 1 other author(s). Microelectron. J., (November 2023)