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In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs.

, , , and . HOST, page 238-247. IEEE, (2019)

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Enhanced Arbiter PUFs using custom sized structures for reduced noise sensitivity., , , and . ICECS, page 568-571. IEEE, (2016)Comparison of Measurement and Readout Strategies for RO-PUFs on Xilinx Zynq-7000 SoC FPGAs., , , , and . ISCAS, page 1-5. IEEE, (2020)In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs., , , and . HOST, page 238-247. IEEE, (2019)Live Demonstration: Generating FPGA Fingerprints Utilizing Full-Chip Characterization with Ring-Oscillator PUFs., , , and . ISCAS, page 1. IEEE, (2020)A 24-Ch. Multi-Electrode Array Allowing Fast EIS to Determine Transepithelial Electrical Resistance., , , , , , and . BioCAS, page 1-4. IEEE, (2019)Modular PUF Coding Chain with High-Speed Reed-Muller Decoder., , , , , , and . ISCAS, page 1-5. IEEE, (2019)Exploiting Weak PUFs From Data Converter Nonlinearity - E.g., A Multibit CT ΔΣ Modulator., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (7): 994-1004 (2016)An Arbiter PUF employing eye-opening oscillation for improved noise suppression., , and . ISCAS, page 1-5. IEEE, (2018)Normalization and Multi-Valued Symbol Extraction From RO-PUFs for Enhanced Uniform Probability Distributions., , , , , and . IEEE Trans. Circuits Syst., 67-II (12): 3372-3376 (2020)Extracting Weak PUFs from Differential Nonlinearity of Digital-to-Analog Converters., , , , , and . ISCAS, page 1-5. IEEE, (2020)