( en | de | ru )

 

Disambiguation of "Ziegler, Matthew M."

Author of the publication

copydeleteadd this publication to your clipboard
Design Flow Parameter Optimization with Multi-Phase Positive Nondeterministic Tuning.

, , and . ISPD, page 29-37. ACM, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Alexander M Ziegler-Jöns

Alexander M Ziegler-Jöns

Matthew Mellon

Matthew David

Matthew Grum

 

Other publications of authors with the same name

The opportunity cost of low power design: a case study in circuit tuning., , , , and . ISLPED, page 133-138. ACM, (2009)LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs., , , , and . ICCAD, page 342-348. IEEE, (2013)Network flow based datapath bit slicing., , , , and . ISPD, page 139-146. ACM, (2013)4.1 22nm Next-generation IBM System z microprocessor., , , , , , , , , and 21 other author(s). ISSCC, page 1-3. IEEE, (2015)Scalable Auto-Tuning of Synthesis Parameters for Optimizing High-Performance Processors., , and . ISLPED, page 180-185. ACM, (2016)POWER8 design methodology innovations for improving productivity and reducing power., , , , , , , , , and 1 other author(s). CICC, page 1-9. IEEE, (2014)Hybrid CMOS/Molecular Electronic Circuits., , and . VLSI Design, page 703-708. IEEE Computer Society, (2006)A synthesis-parameter tuning system for autonomous design-space exploration., , , , , and . DATE, page 1148-1151. IEEE, (2016)Power reduction by aggressive synthesis design space exploration., , and . ISLPED, page 421-426. IEEE, (2013)A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR)., , , , , , , and . PATMOS, volume 5953 of Lecture Notes in Computer Science, page 307-316. Springer, (2009)