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Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits.

C. Yu, X. Zhang, D. Liu, M. Ciesielski, and D. Holcomb. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (10): 1647-1659 (2017)

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Daniel E Gundelfinger

Daniel E Güttinger

Ursula E E Köhler

E Jecht

E Kothe

Other publications of authors with the same name

Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration.M. Usmani, S. Keshavarz, E. Matthews, L. Shannon, R. Tessier, and D. Holcomb. IEEE Trans. Very Large Scale Integr. Syst., 27 (2): 364-375 (2019)Characterizing Power Distribution Attacks in Multi-User FPGA Environments.G. Provelengios, D. Holcomb, and R. Tessier. FPL, page 194-201. IEEE, (2019)Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable Gate Arrays.N. Dumpala, S. Patil, D. Holcomb, and R. Tessier. ACM Trans. Reconfigurable Technol. Syst., 11 (4): 26:1-26:23 (2019)Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits.C. Yu, X. Zhang, D. Liu, M. Ciesielski, and D. Holcomb. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (10): 1647-1659 (2017)Power Distribution Attacks in Multitenant FPGAs.G. Provelengios, D. Holcomb, and R. Tessier. IEEE Trans. Very Large Scale Integr. Syst., 28 (12): 2685-2698 (2020)Remote Power Side-Channel Attacks on CNN Accelerators in FPGAs.S. Moini, S. Tian, J. Szefer, D. Holcomb, and R. Tessier. CoRR, (2020)Remote Power Attacks on the Versatile Tensor Accelerator in Multi-Tenant FPGAs.S. Tian, S. Moini, A. Wolnikowski, D. Holcomb, R. Tessier, and J. Szefer. FCCM, page 242-246. IEEE, (2021)Power Side-Channel Attacks on BNN Accelerators in Remote FPGAs.S. Moini, S. Tian, D. Holcomb, J. Szefer, and R. Tessier. IEEE J. Emerg. Sel. Topics Circuits Syst., 11 (2): 357-370 (2021)Reliable PUF design using failure patterns from time-controlled power gating.X. Xu, and D. Holcomb. DFT, page 135-140. IEEE Computer Society, (2016)Characterization of Long Wire Data Leakage in Deep Submicron FPGAs.G. Provelengios, C. Ramesh, S. Patil, K. Eguro, R. Tessier, and D. Holcomb. FPGA, page 292-297. ACM, (2019)

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Disambiguation of "Holcomb, Daniel E."

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Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits.

Please choose a person to relate this publication to

Daniel E Gundelfinger

Daniel E Güttinger

Ursula E E Köhler

E Jecht

E Kothe

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Holcomb, Daniel E."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits.

Please choose a person to relate this publication to

Daniel E Gundelfinger

Daniel E Güttinger

Ursula E E Köhler

E Jecht

E Kothe

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits.