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A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 54 (11): 2991-3004 (2019)Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits., , , , , , , , and . IEICE Trans. Electron., 93-C (5): 608-613 (2010)An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (2): 109-119 (2016)Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications., , , , , , , , , and 1 other author(s). IEICE Electron. Express, 10 (23): 20130772 (2013)Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme., , , , , , and . ASP-DAC, page 475-476. IEEE, (2012)Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage., , , , , , , , , and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Dependence of tunnel magnetoresistance on ferromagnetic electrode materials in MgO-barrier magnetic tunnel junctions, , , , and . Journal of Magnetism and Magnetic MaterialsVolume 310, (2007)Keywords: Tunnel magnetoresistance; MgO barrier; CoFeB.A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 45 (4): 869-879 (2010)Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 50 (2): 476-489 (2015)MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues., , , , , , and . DATE, page 433-435. IEEE, (2009)