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Disambiguation of "Irita, Takahiro"

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Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor.

, , , , , , , , , , , , , , and . IEEE Micro, 33 (6): 26-36 (2013)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Irita Birzniece

Takahiro Kato

Takahiro Moriyama

Takahiro Kirihara

Takahiro Nishiyama

 

Other publications of authors with the same name

4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems., , , , , , , , , and . ISSCC, page 78-79. IEEE, (2016)A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management., , , , , , , and . ASP-DAC, page 535-539. IEEE, (2009)A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed by Task-Separated ASIL D Control., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 57 (1): 115-126 (2022)A Hardware Accelerator for JavaTM Platforms on a 130-nm Embedded Processor Core., , , , , , , and . IEICE Trans. Electron., 90-C (2): 523-530 (2007)SH-MobileG1: A single-chip application and dual-mode baseband processor., , , , , , , , , and 3 other author(s). Hot Chips Symposium, page 1-24. IEEE, (2006)Self-oscillating chaos generator using CMOS multivibrator., , , and . KES (1), page 213-217. IEEE, (1998)Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor., , , , , , , , , and 5 other author(s). IEEE Micro, 33 (6): 26-36 (2013)A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 44 (1): 83-89 (2009)In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution., , , , , , , and . IEEE J. Solid State Circuits, 42 (4): 784-789 (2007)Microprocessor architecture utilizing redundant-binary operation., , , and . Syst. Comput. Jpn., 30 (13): 106-115 (1999)