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Digital self-correction of time-interleaved ADCs.

, , и . ISCAS (6), стр. 5541-5544. IEEE, (2005)

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A flexible ADC approach for mixed-signal SoC platforms., , , и . ISCAS (5), стр. 4839-4842. IEEE, (2005)Analog Calibration of Mismatches in an Open-Loop Track-and-Hold Circuit for Time-Interleaved ADCs., , , и . ISCAS, стр. 1951-1954. IEEE, (2007)Digital post-correction of front-end track-and-hold circuits in ADCs., , , и . ISCAS, IEEE, (2006)Power Optimization for Pipelined ADCs with Open-Loop Residue Amplifiers., , , и . ICECS, стр. 132-135. IEEE, (2006)A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist., , , , и . ISSCC, стр. 180-182. IEEE, (2011)Design of the Basic Building Block of a High-Speed Flexible and Modular Pipelined ADC., , , и . ISCAS, стр. 3876-3879. IEEE, (2007)Digital self-correction of time-interleaved ADCs., , и . ISCAS (6), стр. 5541-5544. IEEE, (2005)An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals., , , , , , , и . ESSCIRC, стр. 121-124. IEEE, (2013)A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS., , , , и . IEEE J. Solid State Circuits, 46 (12): 2821-2833 (2011)Smart AD and DA converters., , , , , , и . ISCAS (4), стр. 4062-4065. IEEE, (2005)