From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits., , , и . ISCAS, стр. 1484-1487. IEEE, (2010)Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell., , , и . PATMOS, том 3254 из Lecture Notes in Computer Science, стр. 189-197. Springer, (2004)Low-power half-rate dual-loop clock-recovery system in 28-nm FDSOI., , и . LASCAS, стр. 1-4. IEEE, (2018)Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation., , , , и . Microelectron. J., 39 (12): 1663-1670 (2008)Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits., , и . IEEE Trans. Very Large Scale Integr. Syst., 26 (9): 1807-1811 (2018)A Robust 10-Gb/s Duobinary Transceiver in 0.13-μm SOI CMOS for Short-Haul Optical Networks., , , , и . IEEE Trans. Ind. Electron., 65 (2): 1518-1525 (2018)A 1.1-/0.9-nA Temperature-Independent 213-/565-ppm/°C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI., , и . IEEE J. Solid State Circuits, 58 (8): 2239-2251 (2023)Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology., , , , и . IEEE J. Solid State Circuits, 32 (7): 1006-1012 (1997)Design of an Ultra-Low-Power Multi-Stage AC/DC Voltage Rectifier and Multiplier Using a Fully-Automated and Portable Design Methodology., , и . J. Low Power Electron., 8 (2): 197-206 (2012)Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode., , и . IEEE J. Solid State Circuits, 42 (3): 689-702 (2007)