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Disambiguation of "Chen, Pai-Yu"

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Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning.

, , , , , , , , and . ICCAD, page 194-199. IEEE, (2015)

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Pai Tsang Chen

Pai Tsang Chen

Pai Tsang Chen

Yu Chen

Yu Chen

 

Other publications of authors with the same name

Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning., , and . IEEE Trans. Multi Scale Comput. Syst., 2 (4): 257-264 (2016)Low-temperature process in growing carbon nanotube., , and . Microelectron. J., 38 (6-7): 657-662 (2007)Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures., and . IEEE Des. Test, 36 (3): 31-38 (2019)Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing., , , and . ICCAD, page 15. ACM, (2016)Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity., , , , , , , , , and . BICA, volume 41 of Procedia Computer Science, page 126-133. Elsevier, (2014)Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning., , , , , , , , , and . BioCAS, page 536-539. IEEE, (2014)Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing., and . ISCAS, page 2310-2313. IEEE, (2016)Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design., , , and . ISCAS, page 193-196. IEEE, (2015)NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (12): 3067-3080 (2018)Energy-Efficient Adaptive Computing With Multifunctional Memory., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (2): 191-195 (2017)