Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning.

P. Chen, B. Lin, I. Wang, T. Hou, J. Ye, S. Vrudhula, J. sun Seo, Y. Cao, and S. Yu. ICCAD, page 194-199. IEEE, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Tuo Li

Biguang Tuo

Rudolf Tuor

Xihe Tuo

Tuo Liu

Other publications of authors with the same name

Two-dimensional materials for artificial synapses: toward a practical application.I. Wang, C. Chang, Y. Chen, Y. Su, and T. Hou. Neuromorph. Comput. Eng., 2 (1): 12003 (2022)SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices.S. Kingra, V. Parmar, C. Chang, B. Hudec, T. Hou, and M. Suri. CoRR, (2018)Methodology for Realizing VMM with Binary RRAM Arrays: Experimental Demonstration of Binarized-ADALINE using OxRAM Crossbar.S. Kingra, V. Parmar, S. Negi, S. Khan, B. Hudec, T. Hou, and M. Suri. ISCAS, page 1-5. IEEE, (2020)Phase and Carrier Polarity Control of Sputtered MoTe2 by Plasma-induced Defect Engineering.C. Lin, H. Hsu, and T. Hou. DRC, page 1-2. IEEE, (2020)Optimizing Incremental Step Pulse Programming for RRAM Through Device-Circuit Co-Design.J. Liu, T. Wu, and T. Hou. IEEE Trans. Circuits Syst. II Express Briefs, 65-II (5): 617-621 (2018)Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network based on Analog Resistive Synapse.C. Chang, P. Chen, T. Chou, I. Wang, B. Hudec, C. Chang, C. Tsai, T. Chang, and T. Hou. CoRR, (2017)Hardware-Robust In-RRAM-Computing for Object Detection.Y. Chiang, C. Ni, Y. Sung, T. Hou, T. Chang, and S. Jou. IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (2): 547-556 (2022)FPCIM: A Fully-Parallel Robust ReRAM CIM Processor for Edge AI Devices.Y. Guo, W. Lin, T. Hou, and T. Chang. ISCAS, page 1-5. IEEE, (2023)A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration.C. Lin, F. Tsai, J. Su, S. Li, T. Chang, S. Sheu, W. Lo, S. Chang, C. Wu, and T. Hou. A-SSCC, page 1-3. IEEE, (2021)Crossbar array of selector-less TaOx/TiO2 bilayer RRAM.C. Chou, B. Hudec, C. Hsu, W. Lai, C. Chang, and T. Hou. Microelectron. Reliab., 55 (11): 2220-2223 (2015)

BibSonomy

Disambiguation of "Hou, Tuo-Hung"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning.

Please choose a person to relate this publication to

Tuo Li

Biguang Tuo

Rudolf Tuor

Xihe Tuo

Tuo Liu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Hou, Tuo-Hung"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning.

Please choose a person to relate this publication to

Tuo Li

Biguang Tuo

Rudolf Tuor

Xihe Tuo

Tuo Liu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning.