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Disambiguation of "Elshazly, Amr"

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A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method.

, , , , , , , , and . IEEE J. Solid State Circuits, 50 (4): 882-895 (2015)

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Sayed Elshazly

Sami Amr

Amr Allam

Amr Abdelaziz

Amr Hamzawy

 

Other publications of authors with the same name

A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators., , , and . ISSCC, page 464-466. IEEE, (2012)A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer., , , , , , and . ISSCC, page 152-154. IEEE, (2012)A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS., , , , , , and . ISSCC, page 152-154. IEEE, (2011)A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter., , , , and . CICC, page 1-4. IEEE, (2015)A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method., , , , , , , , and . IEEE J. Solid State Circuits, 50 (4): 882-895 (2015)High Frequency Buck Converter Design Using Time-Based Control Techniques., , , , , , , , and . IEEE J. Solid State Circuits, 50 (4): 990-1001 (2015)A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 52 (9): 2306-2320 (2017)15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS., , , , and . ISSCC, page 272-273. IEEE, (2014)A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity., , , and . VLSIC, page 188-189. IEEE, (2012)A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery., , , , , and . IEEE J. Solid State Circuits, 46 (12): 3163-3173 (2011)