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Disambiguation of "Krishnamurthy, Ram"

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Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders.

, , , , and . IEEE Symposium on Computer Arithmetic, page 272-279. IEEE Computer Society, (2003)

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Mahalakshmi Krishnamurthy

Adarsh Krishnamurthy

Arvind Krishnamurthy

Ram Gopal

Johann Ram

 

Other publications of authors with the same name

Dynamic addressing memory arrays with physical locality., , , , and . MICRO, page 161-170. ACM/IEEE Computer Society, (2002)Ultra-low energy circuit building blocks for security technologies., , , and . DATE, page 391-394. IEEE, (2018)Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations., , , , , , and . BioCAS, page 1-5. IEEE, (2017)A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS., , , and . VLSI Design, page 301-306. IEEE Computer Society, (2009)Tutorial: Design of Power Efficient VLSI Arithmetic: Speed and Power Trade-Offs., and . IEEE Symposium on Computer Arithmetic, page 280. IEEE Computer Society, (2003)Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators., , , , and . ARITH, page 84-87. IEEE, (2019)A robust alternate repeater technique for high performance busses in the multi-core era., , , , and . ISCAS, page 372-375. IEEE, (2008)A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array., , , , , , , , , and 2 other author(s). VLSI Circuits, page 238-. IEEE, (2019)A robust edge encoding technique for energy-efficient multi-cycle interconnect., , , , and . ISLPED, page 68-73. ACM, (2007)A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS., , , , , , , , and . CICC, page 1-4. IEEE, (2019)