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A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning.

Z. He, C. Shi, T. Wang, Y. Wang, M. Tian, X. Zhou, P. Li, L. Liu, N. Wu, and G. Luo. IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 1657-1661 (2022)

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Liu Liu

Liyuan Wang-Scheerer

Keetsin Liu

Other publications of authors with the same name

Filling the Gaps in Atrous Convolution: Semantic Segmentation With a Better Context.L. Liu, Y. Pang, S. Zamir, S. Khan, F. Khan, and L. Shao. IEEE Access, (2020)Acceleration of k-Nearest Neighbor Algorithm on FPGA using Intel SDK for OpenCL.L. Liu, and M. Khalid. MWSCAS, page 1070-1073. IEEE, (2018)A 24.3 μJ/Image SNN Accelerator for DVS-Gesture With WS-LOS Dataflow and Sparse Methods.L. Kang, X. Yang, C. Zhang, S. Yu, R. Dou, W. Li, C. Shi, J. Liu, N. Wu, and L. Liu. IEEE Trans. Circuits Syst. II Express Briefs, 70 (11): 4226-4230 (November 2023)Quantizing Oriented Object Detection Network via Outlier-Aware Quantization and IoU Approximation.M. Zhao, K. Ning, S. Yu, L. Liu, and N. Wu. IEEE Signal Process. Lett., (2020)A Programmable and Flexible Vision Processor.Q. Luo, C. Yao, K. Ning, X. Zheng, M. Zhao, L. Cheng, S. Yu, J. Liu, N. Wu, and L. Liu. IEEE Trans. Circuits Syst. II Express Briefs, 69 (9): 3884-3888 (2022)Hierarchical Parallel Vision Processor for High-Speed Ship Detection.M. Xu, Z. Zhang, H. Li, Q. Luo, R. Dou, L. Liu, J. Liu, and N. Wu. IEEE Trans. Circuits Syst. II Express Briefs, 70 (3): 1164-1168 (March 2023)Lightweight zero-knowledge authentication scheme for IoT embedded devices.Z. Wang, J. Huang, K. Miao, X. Lv, Y. Chen, B. Su, L. Liu, and M. Han. Comput. Networks, (November 2023)On the Transformer Growth for Progressive BERT Training.X. Gu, L. Liu, H. Yu, J. Li, C. Chen, and J. Han. NAACL-HLT, page 5174-5180. Association for Computational Linguistics, (2021)A 224-Gb/s Inverter-Based TIA with Interleaved Active-Feedback and Distributed Peaking in 28-nm CMOS for Silicon Photonic Receivers.S. Chen, J. Xue, L. Li, G. Li, Z. Zhang, J. Liu, L. Liu, B. Wang, Y. Li, and N. Qi. ICTA, page 198-199. IEEE, (2022)A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM.X. Shen, Z. Zhang, G. Li, Y. Chen, N. Qi, J. Liu, N. Wu, and L. Liu. ESSCIRC, page 257-260. IEEE, (2023)

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Disambiguation of "Liu, Liyuan"

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A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning.

Please choose a person to relate this publication to

Liu Liu

Liu Liu

Liu Liu

Liyuan Wang-Scheerer

Keetsin Liu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Liu, Liyuan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning.

Please choose a person to relate this publication to

Liu Liu

Liu Liu

Liu Liu

Liyuan Wang-Scheerer

Keetsin Liu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning.