From post

Tera-Scale Performance Machine Learning SoC (MLSoC) With Dual Stream Processor Architecture for Multimedia Content Analysis.

, , , , , и . IEEE J. Solid State Circuits, 45 (11): 2321-2329 (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

Encoder Hardware Architecture for HEVC., , и . High Efficiency Video Coding, Springer, (2014)A 100 MHz 1920×1080 HD-Photo 20 frames/sec JPEG XR encoder design., , , , , , , , , и . ICIP, стр. 1384-1387. IEEE, (2008)Region-of-unpredictable determination for accelerated full-frame feature generation in video sequences., , и . VCIP, стр. 434-437. IEEE, (2014)Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC., , и . ICASSP (5), стр. 9-12. IEEE, (2004)Parallel global elimination algorithm and architecture design for fast block matching motion estimation., , и . ICASSP (5), стр. 153-156. IEEE, (2004)Memory efficient JPEG2000 architecture with stripe pipeline scheme., , , , и . ICASSP (5), стр. 1-4. IEEE, (2005)Low Power Cache Algorithm and Architecture Design for Fast Motion Estimation in H.264/AVC Encoder System., , , , и . ICASSP (2), стр. 97-100. IEEE, (2007)A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm., , , , и . ASP-DAC, стр. 145-150. IEEE, (1998)A hardware-oriented design for weighted median filters., , и . ASP-DAC, ACM, (1995)Design and implementation of JPEG encoder IP core., , , и . ASP-DAC, стр. 29-30. ACM, (2001)