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A high throughput configurable parallel encoder architecture for Quasi-Cyclic Low-Density Parity-Check Codes., , , and . IOLTS, page 163-166. IEEE, (2013)A pure hardware k-SAT solver architecture for FPGA based on generic tree-search., , , , and . ICM, page 1-5. IEEE, (2017)Bearing fault diagnosis based on Alpha-stable distribution feature extraction and wSVM classifier., , , , , and . ICM, page 277-280. IEEE, (2015)Loopback output router for reliable Network on Chip., , , and . IOLTS, page 206-207. IEEE Computer Society, (2011)A New Efficient and Reliable Dynamically Reconfigurable Network-on-Chip., , , and . J. Electr. Comput. Eng., (2012)Characterizing Laser-Induced Pulses in ICs: Methodology and Results., , , , , and . IOLTS, page 11-16. IEEE Computer Society, (2006)A Stamping Technique to Increase the Error Correction Capacity of the (127, k, d) RS Code., , , , and . IOLTW, page 169-170. IEEE Computer Society, (2000)An effective fast and small-area parallel-pipeline architecture for OTM-convolutional encoders., , and . IOLTS, page 257-261. IEEE Computer Society, (2009)CodeRAKE: a new small-area scalable architecture for the multi-user/multi-code RAKE receiver., , , and . ICECS, page 148-151. IEEE, (2006)Stack processor architecture and development methods suitable for dependable applications., , and . ReCoSoC, page 69-75. Univ. Montpellier II, (2007)