Article,
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.
E. Fluhr, S. Baumgartner, D. Boerstler, J. Bulzacchelli, T. Diemoz, D. Dreps, G. English, J. Friedrich, A. Gattiker, T. Gloekler, C. Gonzalez, J. Hibbeler, K. Jenkins, Y. Kim, P. Muench, R. Nett, J. Paredes, J. Pille, D. Plass, P. Restle, R. Robertazzi, D. Shan, D. Siljenberg, M. Sperling, K. Stawiasz, G. Still, Z. Deniz, J. Warnock, G. Wiedemeier, and V. Zyuban.IEEE J. Solid State Circuits, 50 (1): 10-23 (2015)
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- IEEE J. Solid State Circuits
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- 10-23
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- https://doi.org/10.1109/JSSC.2014.2358553
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%1 journals/jssc/FluhrBBBDDEFGGGHJKMNPPPRRSSSSSDWWZ15
%A Fluhr, Eric J.
%A Baumgartner, Steve
%A Boerstler, David W.
%A Bulzacchelli, John F.
%A Diemoz, Timothy
%A Dreps, Daniel
%A English, George
%A Friedrich, Joshua
%A Gattiker, Anne
%A Gloekler, Tilman
%A Gonzalez, Christopher J.
%A Hibbeler, Jason
%A Jenkins, Keith A.
%A Kim, Yong
%A Muench, Paul
%A Nett, Ryan
%A Paredes, Jose
%A Pille, Juergen
%A Plass, Donald W.
%A Restle, Phillip J.
%A Robertazzi, Raphael
%A Shan, David
%A Siljenberg, David W.
%A Sperling, Michael A.
%A Stawiasz, Kevin
%A Still, Gregory S.
%A Deniz, Zeynep Toprak
%A Warnock, James D.
%A Wiedemeier, Glen A.
%A Zyuban, Victor V.
%D 2015
%J IEEE J. Solid State Circuits
%K dblp
%N 1
%P 10-23
%T The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.
%U http://dblp.uni-trier.de/db/journals/jssc/jssc50.html#FluhrBBBDDEFGGGHJKMNPPPRRSSSSSDWWZ15
%V 50
@article{journals/jssc/FluhrBBBDDEFGGGHJKMNPPPRRSSSSSDWWZ15,
added-at = {2022-02-25T00:00:00.000+0100},
author = {Fluhr, Eric J. and Baumgartner, Steve and Boerstler, David W. and Bulzacchelli, John F. and Diemoz, Timothy and Dreps, Daniel and English, George and Friedrich, Joshua and Gattiker, Anne and Gloekler, Tilman and Gonzalez, Christopher J. and Hibbeler, Jason and Jenkins, Keith A. and Kim, Yong and Muench, Paul and Nett, Ryan and Paredes, Jose and Pille, Juergen and Plass, Donald W. and Restle, Phillip J. and Robertazzi, Raphael and Shan, David and Siljenberg, David W. and Sperling, Michael A. and Stawiasz, Kevin and Still, Gregory S. and Deniz, Zeynep Toprak and Warnock, James D. and Wiedemeier, Glen A. and Zyuban, Victor V.},
biburl = {https://www.bibsonomy.org/bibtex/2e046652adad126779f8ed5157251d83a/dblp},
ee = {https://doi.org/10.1109/JSSC.2014.2358553},
interhash = {67ff360ba920f30784a6cb34a8b2fc68},
intrahash = {e046652adad126779f8ed5157251d83a},
journal = {IEEE J. Solid State Circuits},
keywords = {dblp},
number = 1,
pages = {10-23},
timestamp = {2024-04-08T10:44:03.000+0200},
title = {The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc50.html#FluhrBBBDDEFGGGHJKMNPPPRRSSSSSDWWZ15},
volume = 50,
year = 2015
}