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Limited switch dynamic logic circuits for high-speed low-power circuit design.

, , , , , , and . IBM J. Res. Dev., 50 (2-3): 277-286 (2006)

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Undetected disk errors in RAID arrays., , , and . IBM J. Res. Dev., 52 (4-5): 413-426 (2008)Timed circuits: a new paradigm for high-speed design., , , , and . ASP-DAC, page 335-340. ACM, (2001)Evaluating the impact of Undetected Disk Errors in RAID systems., , , , , and . DSN, page 83-92. IEEE Computer Society, (2009)Timed circuit verification using TEL structures., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (1): 129-146 (2001)STOW: A Spatially and Temporally Optimized Write Caching Algorithm., , , and . USENIX Annual Technical Conference, USENIX Association, (2009)Verification of Delayed-Reset Domino Circuits Using ATACS., , and . ASYNC, page 3-12. IEEE Computer Society, (1999)A low latency and low power dynamic Carry Save Adder., , , , , , , and . ISCAS (2), page 477-480. IEEE, (2004)Energy proportionality for storage: impact and feasibility., , , , and . ACM SIGOPS Oper. Syst. Rev., 44 (1): 35-39 (2010)Mercury: bringing efficiency to key-value stores., , , , and . SYSTOR, page 6:1-6:6. ACM, (2013)Cost Effective Storage using Extent Based Dynamic Tiering., , , , and . FAST, page 273-286. USENIX, (2011)