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Limited switch dynamic logic circuits for high-speed low-power circuit design.

W. Belluomini, D. Jamsek, A. Martin, C. McDowell, R. Montoye, H. Ngo, and J. Sawada. IBM J. Res. Dev., 50 (2-3): 277-286 (2006)

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Ngo Hung Manh

Ngo Phuc Hung

Ngo Hung Manh

Other publications of authors with the same name

SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.R. Kanj, R. Joshi, Z. Li, J. Kuang, H. Ngo, N. Zhou, W. Shi, and S. Nassif. ISLPED, page 87-92. ACM, (2008)A 1.0-GHz single-issue 64-bit powerPC integer processor.J. Silberman, N. Aoki, D. Boerstler, J. Burns, S. Dhong, A. Essbaum, U. Ghoshal, D. Heidel, H. Hofstee, K. Lee and 7 other author(s). IEEE J. Solid State Circuits, 33 (11): 1600-1608 (1998)A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction.J. Kuang, H. Ngo, K. Nowka, J. Law, and R. Joshi. ICCD, page 574-584. IEEE Computer Society, (2005)Limited switch dynamic logic circuits for high-speed low-power circuit design.W. Belluomini, D. Jamsek, A. Martin, C. McDowell, R. Montoye, H. Ngo, and J. Sawada. IBM J. Res. Dev., 50 (2-3): 277-286 (2006)Controlled-Load Limited Switch Dynamic Logic Circuit.J. Sivagnaname, H. Ngo, K. Nowka, R. Montoye, and R. Brown. ISQED, page 83-87. IEEE Computer Society, (2005)Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems.J. Sivagnaname, H. Ngo, K. Nowka, R. Montoye, and R. Brown. VLSI Design, page 89-93. IEEE Computer Society, (2006)Design methodology for a 1.0 GHz microprocessor.S. Posluszny, N. Aoki, D. Boerstler, J. Burns, S. Dhong, U. Ghoshal, H. Hofstee, D. LaPotin, K. Lee, D. Meltzer and 5 other author(s). ICCD, page 17-23. IEEE Computer Society, (1998)A low latency and low power dynamic Carry Save Adder.R. Datta, J. Abraham, R. Montoye, W. Belluomini, H. Ngo, C. McDowell, J. Kuang, and K. Nowka. ISCAS (2), page 477-480. IEEE, (2004)Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies.J. Kuang, K. Kim, C. Chuang, H. Ngo, F. Gebara, and K. Nowka. IEEE Trans. Very Large Scale Integr. Syst., 16 (12): 1657-1665 (2008)A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling.K. Nowka, G. Carpenter, E. MacDonald, H. Ngo, B. Brock, K. Ishii, T. Nguyen, and J. Burns. IEEE J. Solid State Circuits, 37 (11): 1441-1447 (2002)

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Disambiguation of "Ngo, Hung C."

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Limited switch dynamic logic circuits for high-speed low-power circuit design.

Please choose a person to relate this publication to

Ngo Hung Manh

Ngo Hung Manh

Ngo Phuc Hung

Ngo Hung Manh

Ngo Hung Manh

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ngo, Hung C."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Limited switch dynamic logic circuits for high-speed low-power circuit design.

Please choose a person to relate this publication to

Ngo Hung Manh

Ngo Hung Manh

Ngo Phuc Hung

Ngo Hung Manh

Ngo Hung Manh

Other publications of authors with the same name

Disambiguation

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URL
DOI
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APA
Chicago
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Limited switch dynamic logic circuits for high-speed low-power circuit design.